The present invention relates to the field of evaluation circuits for passive measurement-variable pickups having ohmic sensor resistors in bridge circuits, wherein adjustment of the output signals of the pickups is made by duration-modulated switching of a resistor which is controlled by an overflow signal of a clock pulse counter into a first switching position, and by the output signal of a digital comparator of the contents of the clock pulse counter and of a sign sensitive voltage/frequency converter into a second switch position. In circuits of this type, the input voltage of the voltage/frequency converter comprises an amplified balancing-difference signal which is rectified by a phase-sensitive rectifier and filtered by a lowpass filter. Furthermore, in circuits of this type, current to the pickups and the switchable resistor are supplied by a polarity-reversing switch controlled by the overflow of the clock pulse counter from a d-c current or voltage source, and the phase-sensitive rectifier is controlled synchronously with the polarity-reversing switch.
Such an evaluation circuit is known from German Pat. No. 22 62 755. The evaluation circuit, described therein as a digital compensating device, is to be, as a result, free of the effects of thermo-voltages and contact potentials in the passive measurement-variable pickups and independent of the null drift of a so-called null amplifier.
In order to obtain a better understanding of the improvements sought by the present invention over the known circuit, it is necessary to analyze the known circuit critically. Therefore, the known circuit is again shown in FIG. 1 herein. In FIG. 1, two measurement-variable pickups DMS-1 and DMS-2 are illustrated which comprise bridge circuits, of which the feed diagonals are supplied with currents IS' via secondary windings of a current transformer Tr1. The measurement diagonals of the measurement variable pickups DMS-1 and DMS-2 are connected in series. The sum voltage present at the diagonals is designated by Um. In opposition to this sum voltage is a compensation voltage Uk, which is formed by the voltage drop across a compensation resistor R.sub.K. The compensation resistor R.sub.K can be connected via a double-throw switch S2 to the secondary winding of a second current transformer Tr2, through which a current IS" flows. A second contact of the double-throw switch S2 is connected to a resistor R.sub.K ' which alternatingly can be connected into a secondary circuit of the transformer Tr2. The primary windings of the current transformers Tr1 and Tr2 are connected in series with a d-c current source U.sub.B via a polarity-reversing switch S1. A current IS flows in the primary windings. The difference between the voltages Um and Uk is fed via lines L1 and L2 to a switch S3 which is connected in series with a null amplifier NV. A second polarity-reversing switch S4 is connected to the output terminals of the null amplifier. Its output terminals are connected via a lowpass filter TP to the input terminals of a voltage/frequency converter SPF. The polarity-reversing switch S4 is actuated synchronously with the polarity-reversing switch S1 so that it acts as a contact rectifier. The output terminals of the voltage/frequency coverter SPF are connected to the forward and backward inputs of a pulse counter Z1. The counting input of a clock pulse counter Z2 is connected to the output of a clock generator TG which furnishes a pulse sequence with the sequence frequency f0. The decade outputs of the counters Z1 and Z2 are connected to comparison inputs of a digital comparison circuit DV. One output of the comparison circuit DV which carries a pulse k indicating agreement of the counter readings z1 and z2, is connected to the input of a switching logic circuit Lo. A transfer pulse u arrives via a connecting line of the highest decade of the clock pulse counter Z2 to a second input of the switching control logic Lo. To a further input of the switching control logic is fed a transfer pulse v of a leading clock counter VZ. One output of the switching control logic controls simultaneously the two double-throw pole switches S1 and S4. Two further outputs of the switching control logic serve for controlling the switches S2 and S3.
Via the switch S1, the polarity of the supply voltage or the supply current, respectively, is changed each time that the clock pulse counter Z2 counts up, due to clock pulses from the clock pulse generator TG to its final counter value .sup.z2 max and delivers a transfer pulse u.
Via the switching control logic Lo, the switch S2 is switched to the resistor R.sub.K ' at the moment at which the clock pulse counter Z2 has the same content as the counter Z1 and therefore, the digital comparison circuit DV indicates by a pulse k the coincidence of the counter readings to the switching control logic Lo. The arithmetic mean Uk of the compensation voltage Uk obtained in this manner is therefore directly proportional to the instantaneous counter reading z1 of the counter Z1, referred to the maximum counter reading .sup.z2 max of the clock pulse counter Z2.
The interrupt switch S3 which is connected through by the switching control logic Lo at the same instant as the switch S2 shifted by the time .DELTA.t relative to the switch reversal points of the feed current, remains connected through during an entire sampling period ##EQU1## to the next transfer pulse u of the clock pulse counter Z2. The null amplifier NV, the input of which is in series with the switch S3, therefore receives the difference voltage .DELTA.U.
It has been found that the desired aims of the above-described circuit can be attained only unsatisfactorily for the following reasons:
In the automatically balancing compensation circuit of FIG. 1, a control loop of closed design is used in which the null amplifier NV, called a control amplifier in control engineering, serves for the amplification of the control deviation as selectivly as is possible. This control deviation will be called here .DELTA.U. It represents the difference of the arithmetic mean values, formed over a switching period T.sub.A, of the sum of the pickup signal voltages Um and the compensation voltage Uk EQU .DELTA.U=Um-Uk
Due to the changed polarity of the supply currents IS which change with every switching of the polarity switch S1, .DELTA.U and all other components of the difference voltage .DELTA.U acting on the input of the null amplifier NV in two successive switching periods T.sub.An and T.sub.An+1 have the opposite sign for the same magnitude. .DELTA.U and .DELTA.U are therefore a-c voltages with a fundamental frequency ##EQU2## without any d-c component.
The following properties are basically required of null amplifiers in control loops:
(a) a high gain in the transmission range of the control deviation; PA1 (b) a null error as small as possible in the amplification of the control deviation; PA1 (c) in the interest of high selectivity and interference suppression, the smallest possible gain outside the transmission range of the control deviation. PA1 (d) a linear control characteristic; PA1 (e) a frequency response with linear phase, and PA1 (f) particular stability of the gain.
Not required, on the other hand, are:
With property (c), a null amplifier such as was used in the known circuit, will exhibit in the transmission range f&lt;f.sub.W an amplitude response dropping as steeply as possible toward lower frequencies and will not transmit particularly the frequency 0 Hz, i.e., d-c voltage signals (highpass characteristic).
This, however, has the consequence, due to the adjustment principle which is used here, namely, the duration-modulated switch reversal, that in the resulting squarewave signals .DELTA.U, slanting tops occur which in turn lead to a nonlinearity of the display characteristic which will be explained below in greater detail.
A lack of property (e), i.e., a frequency response without linear phase in the transmission range f.gtoreq.fW of the null amplifier, results in propogation time distortions in the amplification of the difference signal .DELTA.U. These distortions can lead, in the phase-selective rectification of the amplified difference signal .DELTA.U, to the generation of faulty d-c voltage components by the clock-controlled double-throw switch S4, which are not proportional to the control deviation .DELTA.U and represent null errors.
If property (d) is missing, a linear modulation characteristic, even if the latter has rotary symmetry (without even-numbered curvature terms), positive and negative amplitude sections in the voltage response of .DELTA.U are weighted with different weights. This leads to errors in the formation of the arithmetic mean .DELTA.U of the difference signal which are likewise noted as null errors. The latter, in addition, vary as to magnitude if, as in a conventional null amplifier, also the property (f), especially stability of the gain, is lacking. Since the errors in the formation of the mean are further dependent on the duty cycle a=t.sub.e /T.sub.A, null errors depending on a have an additional effect on the indication characteristic as linearity errors.
The shortcomings caused by the properties of the null amplifier NV are further exacerbated by the potential separation provided by the compensation resistor R.sub.K which can be switched on and off, duration-modulated, for the supply current IS" is compared with the supply current IS' for the measurement-variable pickups by current transformers Tr.
Because of the unavoidable stray inductances of these current transformers as well as the main inductances which can be made only finitely large and the internal resistance, which is only finitely small, of the d-c voltage source which feeds the switch S1, the secondary a-c supply currents IS' and IS" cannot have an ideal squarewave shape. They rather exhibit slanted tops in the form of exponential functions, as is shown in FIG. 2 of the drawings. The following applies to the feed current of the compensation resistor R: EQU IS"(t)=IS"e.sup.-t/.tau.
where .tau. is a time constant which is determined by the values of the stray and main inductances of the current transformer Tr2, the internal resistance of the d-c source and the compensating resistance. In FIG. 2, T.sub.A means the switching duration of a polarity of the double-throw polarity-reversing switch S1, from which results the period T.sub.W =2.times.T.sub.A for the a-c supply currents IS' and IS".
This means that the compensator circuit has a nonlinearity of its display characteristic which no longer satisfies higher accuracy requirements because, according to FIG. 3, the arithmetic mean Uk of the compensating voltage Uk is not proportional over a respective "on" duration T.sub.A, as required by the principle of pulse duration modulation, to the balancing factor a=t.sub.e T.sub.A, the quotient of the "on" time t.sub.e of the compensator resistor R and the switching duration T.sub.A.
We rather have ##EQU3## With Uk=IS".multidot.R.
The definite integral becomes ##EQU4## and, after a series development of ##EQU5## with a=t.sub.e /T.sub.A, this becomes ##EQU6##
As is shown in FIG. 3, the compensation voltage Uk is not proportional to a=t.sub.e /T.sub.A according to the series expression above, but is less than linear with a linearity error F.sub.Lin which is the larger, the smaller the time constant of the top slant as compared to the switching duration T.sub.A.
On the other hand, the arithmetic mean Um is formed by the sum Um of the output voltages U.sub.m.nu. of all n measurement variable pickups DMS.sub..nu. by the known compensator circuit always over the full switching time T.sub.A, i.e., ##EQU7## With this, one gets ##EQU8## With ##EQU9## where c.sub.v means a pickup sensitivity constant. Thus, the mean Um is proportional strictly linearly, because of the purely ohmic networks in the pickups DMS.sub.v in spite of the top slants, embodied by, of the individual signals Um.sub.v of the sum of the measurement variables G.sub.v acting at any instant on the n pickups DMS.sub.v.
The display indication value A which is proportional to the duty cycle a=t.sub.e /T.sub.A of the known compensator circuit is obtained via the balance condition EQU Uk(a)=Um(.epsilon.G.sub.v).
Because of the underlinearity of Uk, the known compensator circuit must therefore have as a whole an overlinear display characteristic.